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PHK13N03LT trenchmos? logic level fet rev. 01 23 june 2003 product data m3d315 1. product pro?le 1.1 description n-channel enhancement mode ?eld-effect transistor in a plastic package using trenchmos? technology. product availability: PHK13N03LT in sot96-1 (so8). 1.2 features 1.3 applications 1.4 quick reference data 2. pinning information n low gate charge n surface mount package n low on-state resistance n fast switching. n portable appliances n notebook computers n lithium-ion battery chargers n dc-to-dc converters. n v ds 30 v n i d 13.8 a n p tot 6.25 w n r dson 20 m w table 1: pinning - sot96-1 (so8), simpli?ed outline and symbol pin description simpli?ed outline symbol 1,2,3 source (s) sot96-1 (so8) 4 gate (g) 5,6,7,8 drain (d) 4 5 1 8 top view mbk187 s d g mbb076
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 2 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. 3. limiting values table 2: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage (dc) 25 c t j 150 c - 30 v v dgr drain-gate voltage (dc) 25 c t j 150 c; r gs =20k w -30v v gs gate-source voltage (dc) - 20 v i d drain current (dc) t sp =25 c; v gs =10v; figure 2 and 3 - 13.8 a t sp = 100 c; v gs =10v; figure 2 - 8.7 a i dm peak drain current t sp =25 c; pulsed; t p 10 m s; figure 3 -55a p tot total power dissipation t sp =25 c; figure 1 - 6.25 w t stg storage temperature - 55 +150 c t j junction temperature - 55 +150 c source-drain diode i s source (diode forward) current (dc) t sp =25 c - 5.7 a i sm peak source (diode forward) current t sp =25 c; pulsed; t p 10 m s - 55 a
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 3 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. v gs 3 5v fig 1. normalized total power dissipation as a function of solder point temperature. fig 2. normalized continuous drain current as a function of solder point temperature. t sp =25 c; i dm is single pulse fig 3. safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa17 0 40 80 120 0 50 100 150 200 (%) t sp ( c) p der 03aa25 0 40 80 120 0 50 100 150 200 t sp ( c) i der (%) p der p tot p tot 25 c () ----------------------- 100 % = i der i d i d25c () ------------------- 100 % = 003aaa487 10 -1 1 10 10 2 10 -1 1 10 10 2 v ds (v) i d (a) dc 100 ms 10 ms 1 ms t p = 10 m s 100 m s limit r dson = v ds /i d
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 4 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. 4. thermal characteristics 4.1 transient thermal impedance table 3: thermal characteristics symbol parameter conditions min typ max unit r th(j-sp) thermal resistance from junction to solder point figure 4 --20k/w r th(j-a) thermal resistance from junction to ambient minimum footprint; mounted on a printed-circuit board - 70 - k/w fig 4. transient thermal impedance from junction to solder point as a function of pulse duration. 003aaa324 10 -1 1 10 10 2 10 -4 10 -3 10 -2 10 -1 1 10 (k/w) single pulse 0.2 0.1 0.05 d = 0.5 0.02 t p t p t p t t d = t p (s) z th(j-sp)
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 5 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. 5. characteristics table 4: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d = 250 m a; v gs =0v t j =25 c 30--v t j = - 55 c 27--v v gs(th) gate-source threshold voltage i d = 250 m a; v ds =v gs ; figure 9 v t j =25 c 1 1.5 2 v t j = 150 c 0.5 - - v t j = - 55 c - - 2.2 v i dss drain-source leakage current v ds =24v; v gs =0v t j =25 c --1 m a t j = 100 c --5 m a i gss gate-source leakage current v gs = 20 v; v ds = 0 v - - 100 na r dson drain-source on-state resistance v gs = 10 v; i d =8a; figure 7 and 8 t j =25 c - 17 20 m w t j = 150 c --33m w v gs = 4.5 v; i d =7a; figure 7 - 2126m w dynamic characteristics q g(tot) total gate charge i d = 8 a; v dd =15v; v gs =5v; figure 13 - 10.7 - nc q gs gate-source charge - 2.7 - nc q gd gate-drain (miller) charge - 3.9 - nc c iss input capacitance v gs =0v; v ds = 15 v; f = 1 mhz; figure 11 - 752 - pf c oss output capacitance - 200 - pf c rss reverse transfer capacitance - 130 - pf t d(on) turn-on delay time v dd =15v; i d = 1.5 a; v gs =10v; r g =6 w -6-ns t r rise time -7-ns t d(off) turn-off delay time - 23 - ns t f fall time -11-ns source-drain diode v sd source-drain (diode forward) voltage i s = 7 a; v gs =0v; figure 12 - 0.86 1.1 v t rr reverse recovery time i s = 7 a; di s /dt = - 100 a/ m s; v r =30v; v gs =0v -25-ns q r recovered charge - 5 - nc
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 6 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. t j =25 ct j =25 c and 150 c; v ds > i d xr dson fig 5. output characteristics: drain current as a function of drain-source voltage; typical values. fig 6. transfer characteristics: drain current as a function of gate-source voltage; typical values. t j =25 c fig 7. drain-source on-state resistance as a function of drain current; typical values. fig 8. normalized drain-source on-state resistance factor as a function of junction temperature. 003aaa325 0 2 4 6 8 10 0 0.5 1 1.5 2 v ds (v) i d (a) 2.5 v 2.3 v 2.4 v 2.6 v v gs = 2.8 v 2.7 v 3 v 10 v 5 v 003aaa326 0 2 4 6 8 10 0123 v gs (v) (a) v ds > i d x r dson i d t j = 150 c 25 c 003aaa327 0 20 40 60 80 0246810 i d (a) r dson (m w ) 10 v 2.6 v 2.5 v 3 v 5 v 4 v v gs = 2.8 v 03aa27 0 0.5 1 1.5 2 -60 0 60 120 180 t j ( c) a a r dson r dson 25 c () ---------------------------- - =
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 7 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. i d = 1 ma; v ds =v gs t j =25 c; v ds =5v fig 9. gate-source threshold voltage as a function of junction temperature. fig 10. sub-threshold drain current as a function of gate-source voltage. v gs = 0 v; f = 1 mhz fig 11. input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03aa33 0 0.5 1 1.5 2 2.5 -60 0 60 120 180 t j ( c) v gs(th) (v) max typ min 003aaa426 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 012 3 v gs (v) i d (a) max typ min 003aaa328 10 10 2 10 3 10 4 10 -1 1 10 10 2 c (pf) c iss c oss c rss v ds (v)
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 8 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. t j =25 c and 150 c; v gs =0v i d = 8 a; v dd =15v fig 12. source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. fig 13. gate-source voltage as a function of gate charge; typical values. 003aa a329 0 2 4 6 8 0.2 0.4 0.6 0.8 1 v sd (v) i s (a) t j = 150 c 25 c 003aaa330 0 1 2 3 4 5 0 5 10 15 q g (nc) v gs (v)
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 9 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. 6. package outline fig 14. sot96-1 (so8). unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
philips semiconductors PHK13N03LT trenchmos? logic level fet product data rev. 01 23 june 2003 10 of 12 9397 750 11611 ? koninklijke philips electronics n.v. 2003. all rights reserved. 7. revision history table 5: revision history rev date cpcn description 01 20030623 - product data (9397 750 11611)
9397 750 11611 philips semiconductors PHK13N03LT trenchmos? logic level fet ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 01 23 june 2003 11 of 12 9397 750 11611 philips semiconductors PHK13N03LT trenchmos? logic level fet ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 01 23 june 2003 11 of 12 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 8. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 9. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 10. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 11. trademarks trenchmos is a trademark of koninklijke philips electronics n.v. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2003. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 23 june 2003 document order number: 9397 750 11611 contents philips semiconductors PHK13N03LT trenchmos? logic level fet 1 product pro?le . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 1 3 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 thermal characteristics. . . . . . . . . . . . . . . . . . . 4 4.1 transient thermal impedance . . . . . . . . . . . . . . 4 5 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 8 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 9 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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